The present invention relates to the field of programmable and other such devices, as well as systems and methods for programming the same.
Programmable devices, such as field programmable gate arrays (FPGAs), typically include thousands of programmable logic cells that use combinations of logic gates and/or look-up tables to perform logic operations. Programmable devices typically also include a number of functional blocks having specialized logic devices adapted to specific logic operations, such as adders, multiply and accumulate circuits, phase-locked loops, and one or more embedded memory array blocks. The logic cells and functional blocks typically are interconnected with a configurable switching circuit, which selectively routes connections between the logic cells and functional blocks. By configuring the combination of logic cells, functional blocks, and the switching circuit, a programmable device can be adapted to perform virtually any type of information processing function.
Programmable devices typically include one or more input/output (I/O) banks for communication with external devices, such as memory devices, network interfaces, data buses and data bus controllers, microprocessors, other programmable devices, application-specific integrated circuits (ASICs), or virtually any other type of electronic device. Each I/O bank is connected with a number of conductive I/O pins, balls, or other electrical connectors in the programmable device chip package. An I/O bank includes logic for sending and receiving data signals, control signals, or any other type of signal used in conjunction with communications between the programmable device and an external device.
The I/O banks of a programmable device typically include input and output buffers registers, flip flops, serial-to-parallel and parallel-to-serial converters, and control circuits and other circuits that together can be configured to provide one or more standard interfaces between the programmable device and external devices. Additionally, the I/O banks of a programmable device may be configured to provide custom or proprietary interfaces for a particular application.
In various configurations, the state of each data pin (e.g., DQ pin) in an I/O bank can be latched into registers upon the leading edge of a corresponding clock signal (e.g., DQS signal). For double data rate (DDR) interfaces, the pins can be allowed to switch again per the predetermined switching cycle, then have their values latched again upon the falling edge of the DQS signal (hence the double data rate). In order to avoid latching at or near the time that the data is switching, the data typically is latched using a clock signal that is phase shifted by 90° degrees so that the data is latched approximately half-way between switching times, typically referred to as the middle of the “eye” or “window.” At startup of an FPGA device, for example, a data training cycle or other calibration process can be used to calibrate a sampling clock for read and/or write operations, putting the clock edges in the middle of valid windows.
Operations such as accessing an external memory after startup, however, can affect the timing performance of the device. For example, executing a number of read and write cycles tends to increase the temperature of the programmable device and affect the operating voltage levels across the device. The environmental temperature also can greatly affect the delay times for a device. These variations in temperature and voltage can affect numerous aspects of the device, such as the delay time encountered by a signal passing through a signal path on the device.
One way to address this problem is simply to use periodic data training cycles to re-calibrate the sampling clock, or at least to track changes due to factors such as voltage and temperature. Reading back training patterns while the user is reading and writing to the memory imposes on the user, though, which breaks the “transparency rule” for such devices. Transparency rules refer to requirements that processes be “transparent” to a user, in that the user does not notice the processes and the processes do not significantly interfere with user and/or device operation.
It therefore is desirable to allow for tracking and/or adjustment of these sampling clocks during operation of a programmable device, with the tracking and/or adjustment being transparent to a user of the device.